This invention relates to semiconductor memory devices, and more particularly to an organization for a high density dynamic metal-oxide-semiconductor (MOS) random access memory (RAM) having an array of one transistor, one capacitor memory cell.
MOS dynamic RAMs are known in the art. These memories are fabricated on a single silicon chip using known MOS technologies. Typically, n-channel MOS technology is used because of its inherent performance advantages. In recent years there has been a rapid evolution of MOS dynamic RAMs toward increased density and higher performance. Each new generation of RAMs has provided a four-fold increase in storage capacity over those of the previous generation. This evolution has been made possible by advances in n-channel MOS technology and in wafer patterning techniques leading toward a shrinkage in the size of the memory cell. Today MOS RAMs having a storage capacity of 16,384 bits (i.e., 16K RAMs) are commercially available. Presently, manufacturers are starting to introduce a 65,536 bit, or 64K, RAM; see Electronics, Sept. 28, 1978, pp. 109 to 116.
One important consideration in the design of a high density dynamic RAM is that of providing adequate signal for sensing. As mentioned above, RAMs of higher density are made possible by reducing the size of the memory cell. However, decreasing the cell size also decreases its storage capacitance. Moreover, as an increased number of cells are included in the array, the number of cells coupled to a bit-line (column conductor) is increased. Therefore, the capacitance of the bit-line is also increased. Inasmuch as the magnitude of the data signal presented to a sense amplifier is proportional to the ratio of the storage capacitance of the cell to the capacitance of the bit-line, it is clear that this ratio must be kept as high as necessary to insure an adequate signal for sensing.
A technique for reducing the bit-line capacitance which is widely used in commercially available 16K RAMs is described in IEEE Journal of Solid State Circuits, October 1976, pp. 570-573 by Ahlquist et al. The technique is to divide the array of memory cells into two sub-arrays. For example, in the case of a 16K RAM instead of using a single array of 128 rows and 128 columns, two arrays of 64 rows and 128 columns are used. Accordingly, the number of cells coupled to each bit-line is reduced from 128 to 64, and thus the bit-line capacitance is reduced by a factor of two while the data signal presented to a sense amplifier is increased by the same factor. Therefore, it is known in the art that by dividing a memory array into sub-arrays, the bit-line capacitance may be reduced.
Another important consideration in the design of a new generation high density RAM is that of compatibility with previous generation RAMs. For example, important commercial advantages are gained by designing a 64K RAM to be compatible with industry standard 4K or 16K RAMs to permit users to directly substitute in their memory systems 64K parts for 4K or 16K parts without having to redesign their systems. In general, compatibility is important in the areas of package type and size, assignment of package pin functions, and in the number of refresh cycles required by the RAM.
Refreshing of a dynamic RAM is accomplished by sensing and restoring the voltage levels present on each cell in the memory array. This is normally done one row at a time so that the number of cycles required is equal to the number of rows in the array. Normally, each time a row in the array is selected all cells along the row are automatically refreshed. Therefore, one way to achieve compatibility in the number of refresh cycles is for the new generation RAM to have the same number of rows as a previous generation RAM. For example, the array of the 16K RAM described in the above-identified Ahlquist et al reference has a total of 128 rows in two sub-arrays. Thus if the array is refreshed one sub-array at a time then 128 refresh cycles would be required which is the industry standard refresh sequence for a 16K RAM. However, the sub-arrays in the Ahlquist RAM can also be refreshed in parallel; that is, corresponding rows in each sub-array can be refreshed at the same time. In the case of a 64K RAM a straightforward 256 row by 256 column array would result in a 256 cycle refresh sequence which would make it incompatible with the industry standard 16K RAM.
One possible organization for a 64K RAM for providing a 128 cycle refresh sequence is to have a single array of 128 rows and 512 columns. However, such an organization would result in a memory chip having an awkward aspect ratio, and one which would not fit into the industry standard 16 pin package used by 16K RAMs. A more favorable chip aspect ratio may be obtained for the 64K RAM by using an organization having two sub-arrays of 128 rows and 256 columns in which a row in each sub-array is simultaneously selected in a given operating cycle. An operating cycle is an interval during which a memory function such as reading, writing, refreshing or a combination thereof takes place in the RAM. Since a row in each sub-array is refreshed in each refresh cycle, 128 refresh cycles are sufficient to refresh the entire RAM. Therefore, dividing the memory array into sub-arrays provides the flexibility necessary to achieve compatibility between old and new generation RAMs.
A major consideration in the design of a high density RAM is that of minimizing the power dissipation of the memory chip. Additional circuits and larger loads associated with chips having a larger number of cells result in increased power dissipation. However, the above-mentioned compatibility consideration that the new generation RAM be a direct substitute for older generation RAMs in existing memory systems which were designed according to the power specifications of older generation RAMs imposes a critical restriction on the power dissipation of the new generation RAM. Therefore, a major problem in high density RAM design is that of limiting power dissipation.
An arrangement for reducing power dissipation in a 16K RAM organized in two sub-arrays described in the above-cited Ahlquist et al. paper is to activate only one sub-array in a given operating cycle and to keep the other sub-array totally inactive. Thus, power dissipation is reduced below that of an arrangement where both sub-arrays are active. However, the arrangement described in Ahlquist is restricted to a memory organization where memory function takes place in only one sub-array in any given operating cycle, and would not be applicable to the organization described above for a 64K RAM where a row in each sub-array is refreshed in any given operating cycle.